Saelig Company has introduced the Ikalogic SP2 series of compact nine-channel 200 MHz logic analyzers, which offer analysis of logic signals and protocol decoding with 200 MHz (5 ns) timing resolution. The nine channel design allows 8-bit parallel data to be captured along with a clock or strobe signal at the maximum sampling rate without any trade-off between the number of active channels and the sampling rate. This is possible due to an embedded 2 Gb memory that buffers the captured signals before sending to the attached PC.

The SP2 series analyzes CMOS logic signals and industrial buses. The series consists of two devices: the SP209 is the standard edition and the SP209i is an industrial version with specialized receivers for most common industrial busses, like RS485, RS232 or CAN. The trigger-in and trigger-out SMA connectors allow users to synchronize the SP209 to other lab equipment, building highly sophisticated test setups. The Spartan 6 FPGA design provides the processing power required and can easily be firmware-updated.

The SP2 series logic analyzers use the supplied ScanaStudio software (Windows, Mac and Linux) to capture, display, analyze and decode signals. Most industry standard protocols can be decoded, including: SPI, I2C, USART, 1-Wire, CAN, LIN, I2C, RS232, RS485, TWI and more. The software captures long sequences of logic signals or view decoded signals in various levels of abstraction. It also targets specific events due to the versatile multi-stage trigger system. The SP2 series logic analyzers compress and stream captured signals via USB 2.0 to an attached Windows, Linux or MacOS computer. USB bandwidth can be variable from system to system, with a practical limitation of 20 MB/s. SP2 logic analyzers have an embedded 2Gb DDR-3 memory which buffers captured samples at 1.6GB/s to avoid these USB limitations.

For detailed specifications, free technical assistance or additional information, please visit www.saelig.com.